1. Field of the Invention
The invention relates to wireless RF transceivers, and more particularly to integrated direct conversion transceiver (DCT) front ends with real-time DC offset tracking and cancellation.
2. Description of the Related Art
The applications of RF transceivers have been accompanied with aggressive goals: low cost, low power dissipation, and small form factor. The architecture for wireless transceivers includes three types: superheterodyne, low IF and direct conversion (zero IF). Among them, direct conversion perhaps is the most suitable architecture for IC implementation. The reason is three fold. 1) Direct conversion, in principle, lends itself to monolithic integration much more easily than do others; 2) Direct conversion suffers much less from mismatch-induced effects than does low IF architecture, 3) The integration of direct conversion offers small area, low power consumption, and thus low cost. Refer to    B. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 428–435, June 1997.    A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE Journal of 1997.Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, December 1995.It follows that direct Conversion Transceivers (DCT) appear more and more promising and profitable both in the academic world and in industry. Although DCT has many matchless merits, there exist some fatal drawbacks which have prevented its wide usage for many years. These factors mainly include DC offset, I/Q mismatch, even-order distortion, and flicker noise etc, per the above two references. Among these, the DC offset problem may be the biggest one for the DCT in practical applications.
As shown in FIG. 1a (same as FIG. 4 of reference B. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 6, pp. 428–435, June 1997), the DC offset is mainly produced by self-mixing of downcoversion mixers. Block 11 is a a low noise amplifier (LNA) 11 receiving RF input port A and coupled to mixer 12. The low pass filter (LPF) 13 is coupled to amplifier 14, which coupled to analog-to digital converter (ADC) 15. Local oscillator (LO) is an input, with signal cos ωLOt, to mixer 12. This self-mixing comes from two factors. The first is due to the LO leakage. Owing to the limited isolation between RF input port A and LO input port of mixers (because of various capacitive and substrate coupling, external bonding wire coupling etc.), the leakage signal appearing at the mixer RF input B will self mix with the LO signal, and thus DC offset is produced.
The second is due to the RF interference leakage, as illustrated in FIG. 1b and described next. Note that the same numerals in FIGS. 1a and 1b designate the same component. The received RF signal will also leak to the LO port and then self mixes with itself, which produces undesired DC offset. The DC offset includes fixed as well as time-varying components. Typically, the DC offset signal is larger than the desired signal by 30–40 dB at the mixer output. The gain stage after the mixer provides ˜70 dB gain. Thus, if directly amplified by the following stage, the DC offset voltage will block the VGA, and thus prohibits the amplification of the useful signal. As will become apparent in the following text, a practical technique is disclosed which overcomes effectively the DC offset problems for DCT applications.
In the literature, there are already some methods to overcome DC offset problems in DCT. Sub-harmonic mixers and/or even harmonic mixers have been used to overcome the DC offset problems, as discussed in references    T. Yamaji and H. Tanimoto, “A 2 GHz Balanced Harmonic Mixer for Direct Conversion Receivers,” IEEE customer integrated circuit conference, pp. 193–196, 1997 and    Z. Zhang, Z, Cheng and Jack Lau, “A 900 MHz CMOS Balanced Harmonic Mixer for Direct Conversion Receivers,” IEEE CICC, pp. 219–222, 2000.Although these methods can be employed to alleviate the problems in DCT, specific circuit architecture and extra clock circuit have to be used, which cannot ensure to work with high performance in practical applications.
A multiphase frequency synthesizer is also used to provide a LO signal which does not produce the self-mixing and thus can alleviate the DC offset problems in    K. Lee et al. “A Single Chip 2.4 Ghz Direct Conversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique,” IEEE Journal of Solid-State Circuits, vol. 36, no. 5, pp. 800–809, May 2001.However, this technique requires a complex PLL circuit and high implementation cost. In the IF domain, to overcome the DC offset problem, three methods have been proposed. One is AC coupling and lowpass-highpass filtering. Refer to    B. Razavi, “A 2.4 GHz CMOS Receiver for IEEE 802.11 Wireless LAN's,” IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1382–1385, October 1999.This method can filter out of fixing DC offset due to LO leakages but cannot overcome the time-varying DC offset components. The second is the servo feedback amplifier which can track and tackle all kinds of DC offsets. See    A. Parssinen etc., “A Wide-Band Direct Conversion Receiver for WCDMA Applications,” ISSCC99, pp. 220–221, 1999 and    C. D. Hull, J. L. Tham and R. R. Chu, “A Direct-Conversion Receiver for 900 MHz (ISM Band) Spread Spectrum Digital Cordless Telephone,” IEEE Journal of Solid-State Circuits, vol. 31, no. 12, pp. 1955–1963, December 1996.However a large capacitor (˜100 nF) has to be used which cannot be integrated and occupies a large area.
The last is the digital signal processor (DSP) feedback compensation method. See references    J. K. Cavers and M. W. Liao, “Adaptive Compensation for Imbalance and Offset Losses in Direct Conversion Transceivers,” IEEE Transactions on vehicular technology, vol. 42, no. 4, November 1993, pp. 581–588.    B. Lindoff and P. Malm, “BER Performance Analysis of Direct Conversion Receiver,” IEEE Transactions on Communications, vol. 50, no. 5, pp. 856–865, May, 2002, and    W. Namgoong and T. H Meng, “Direct-Conversion Rf Receiver Design,” IEEE Transactions on Communications, vol. 49, no. 3, pp. 518–529, March 2001.This method can accurately estimate the DC offset in the baseband and then cancel them in the analog domain. The main shortcoming of this method is that it has to employ an extra ADC/DAC circuit and baseband signal processing circuit so that the implementation cost is high. Since closed loop feedback tuning has to be used, the problem of loop setting time and stability need to be carefully designed for this method.
The forward DC offset and IM2 interference cancellation maybe done using adaptive filtering algorithm in the baseband as discussed in    M. Faulkner, “DC offset and IM2 removal in direct conversion receivers,” IEE Proc. Communication, vol. 149, no. 3, June 2002, pp. 179–184.However, the algorithm complexity and speed have to be compromised with the performance. To achieve real-time DC offset tracking and cancellation, a simple algorithm but with good performance has to be developed.
U.S. Patents or U.S. Patent Applications relating to the subject at hand are:    In U.S. Pat. No. 6,516,185 (MacNally), DC offset canceling is done through a variable gain amplifier. The feed forward canceller is used.    In U.S. Patent Application Publication 0,062,951 (Twomey), through current splitting and tuning, a mixer/amplifier circuit is invented capable of providing variable gain while maintaining a substantially constant common mode operating voltage level.    In U.S. Pat. No. 6,335,656 (Goldfarb et al.), the DC offset is canceled by a series of highpass filters which have lower and lower cutoff frequencies.    In U.S. Pat. No. 6,407,630 (C. T. Yao et al.) a DC offset canceling circuit is integrated with a VGA. Large capacitors have to be used in the feedback loop to store and cancel the DC offset at the input of VGA.    In U.S. Patent Application Publication 0,181,619 (E. W. McCune JR.), the LO signal is adaptively adjusted to be in quadrature with RF signals so that the DC offset can be canceled. The accuracy of this method is limited by the matching of circuits in practical applications.    In U.S. Pat. No. 6,504,884 (Zvonar) a method is proposed which can estimate the DC offset as well as the channel impulse response in baseband. Both the DC offset and channel ISI can be overcome. This method is suitable to eliminate the small residue DC offset in baseband but cannot deal with the large DC offset in an RF front-end.    In U.S. Pat. No. 5,918,167 (Tiller et al.,) the DC offset is detected in the mixer output and then fed back to the mixer input to cancel the DC offset. Since low pass filter (LPF) and automatic gain control (AGC) circuits have to be used, the DC cancellation accuracy will be limited by the choice of LPF cutoff frequency and AGC dynamic range and resolution.    In U.S. Pat. No. 6,535,725B2 (G. Hatcher et al.) DC offset is detected at the input of mixers. A compensator is used to cancel the DC offset at the output of the mixers. To detect the DC offset, an extra known interference testing signal has to be employed. The compensator includes a complex controller and a corrector. Thus the whole cost of the DC offset cancellation system is high. Moreover, the DC offset cancellation accuracy of this patent is limited by the adjusting step size (minimum current bit).    In U.S. Pat. No. 6,148,184 (T. Manku et al.) quadrature baseband signals are produced by mixing a RF signal with quadrature LO signals. A total of six mixers is needed for I/Q downconversion. To overcome DC offset, LO signals have to be modulated by an extra phase modulated (PM) signal. The performance of the patent is limited by the choice of the frequency of PM signals and phase accuracy between mixer M1(M2) and mixer M3.
To overcome the problems and disadvantages of the above cited related art, we are proposing the following solutions:
(1) a new architecture named DC Offset-Free DCR RF Front-End with Symmetrical Mixer to overcome the DC offset problem. Through this new architecture the desired signal will be enhanced and the DC offset will be cancelled automatically at the output of the RF front-end of a direct-conversion receiver. In contrast to the methods of the related art above, the common mixers such as the Gilbert cell can be adopted and no specific circuit is needed. The DC offset cancellation performance is guaranteed both in theory and simulation, and its actual performance is only limited by the process mismatch in practical applications.
(2) a new RF Front-End DC Offset Feedback Tuning Loop circuit which can combine the RF front-end with baseband tuning circuits to overcome DC offsets when viewed as a system. A feedback tuning loop circuit is developed which can detect the DC offset in the analog baseband and then feeds back the tuning voltage to RF mixers to cancel the DC offset. The current-tuning technique of active mixers is proposed here for the first time and can track the time-varying DC offset and cancel it in real-time. The complete DC offset cancellation technique, by integrating these two methods in a direct conversion receiver, not only can cancel large (burst) and small DC offset due to LO and/or RF leakage, but also can overcome the time-varying DC offset when the receiver moves, i.e., changes physical location (such as a person carrying a cell-phone in a car for example). No external capacitor and components are needed. The proposed front-end can be implemented in low cost processes, such as CMOS, but with high performance (high DC offset rejection, fast setting time, etc.).